For realizing very efficient electric power control, the markets have been requiring a reduction in conduction losses, i.e. a reduction in the on-resistance, of semiconductor devices for electric power control, which are the so-called power semiconductor devices. For reducing the on-resistance in the power MOSFETs and the power IGBTs, the cells in the active section of the semiconductor substrate (chip), through which a main current flows, are made smaller such that the cell pitch in the semiconductor chip is narrow.
The semiconductor devices described above have a planar MOS gate structure formed along the major surface of the semiconductor chip. Power semiconductor devices such as trench MOSFETs and trench IGBTs that facilitate reducing the on-resistance greatly have been known. The trench MOSFETs and the trench IGBTs have a trench MOS gate structure. The trench MOS gate structure includes trenches formed in a semiconductor substrate, which extend perpendicularly to the major surface thereof and a gate electrode buried in each of the trenches with a gate insulator film interposed between the gate electrode and the trench. The trench MOS gate structure facilitates forming channels in the surface portions of the semiconductor substrate on both sides of the trenches such that the channels are facing the gate electrodes. The trench MOS gate structure, which facilitates forming channels as described above, has facilitated an epoch-making narrowing of the cell pitch and a great reduction of the on-resistance.
For further minimizing the cells and for further increasing the cell density in the trench MOS gate structure described above, it is necessary to establish reliable techniques for reducing the trench width. However, the conventional techniques for reducing the trench width pose many problems. For forming fine trenches, narrower than 2 μm in width, especially narrower than 1 μm in width, and around 6 μm in depth, it is difficult to control the shape of the trenches, to remove the crystal defects caused in the trench inner walls, to remove the etching residues left in the trenches, and to clean the inside of the trenches, posing new problems. In detail, when the inner surfaces of the trenches are treated using a dilute solution of hydrofluoric acid and such a chemical reagent, it is difficult for the dilute solution to reach deep into the depth of the trenches. It is also difficult for the pure water used for washing subsequently to the surface treatment to reach into the depth of the trenches. In the drying step subsequent to the etching step, it is difficult to purge the chemical solution or the pure water described above from the trenches. If the trenches are not washed well, the residues and the crystal defects remaining in the trenches lower the breakdown voltage of the gate insulator films and impair the reliability of the gate insulator films, since the gate electrodes are formed in the trenches, in which the residues and the crystal defects are remaining, with the respective gate insulator films interposed between the gate electrodes and the trenches. Low breakdown voltage and low reliability of the gate insulator films due to the remaining residues and crystal defects, pose serious problems to be obviated, especially for minimizing the trenches so that the width thereof may be 1 μm or narrower.
In forming the trenches with a width of 1 μm or narrower, the gate breakdown voltage is lowered and the reliability thereof is impaired due to the poor cleaning of the trench interiors. In addition, it is more difficult to control the shape of the trenches, whose widths are 1 μm or narrower, than to control the shape of the conventional trenches, whose widths are wider than 1 μm. When the trench has the conventional shape, 1 or 2 μm wider in width, the electric field is liable to localize at the trench corners, which impairs the breakdown voltage due to the angularity of the trench corners. It has been known that excellent results are obtained for preventing the breakdown voltage and the reliability of the gate from being impaired, by rounding the trench corners and smoothing trench surfaces roughened by the etching, using a heat treatment technique in a non-nitriding and non-oxidizing atmosphere, for example a heat treatment technique in a hydrogen atmosphere. Such a heat treatment technique is described in OYO BUTURI (a Japanese monthly publication of The Japan Society of Applied Physics) (2000), Vol. 69, No. 10, pp. 1187-1191. This technique facilitates smoothing the surface roughness of a 100 nm level to the surface roughness of a 10 nm level. The OYO BUTURI publication describes the heat treatment technique in a hydrogen atmosphere to be effective for trench shaping control. The OYO BUTURI publication reports also that it is possible for this above-described heat treatment technique to reduce the crystal defects and to remove the oxide residues of SiOX to some extent. However, this above-described heat treatment technique poses problems when the trenches are 2 μm or narrower in width and especially when the trenches are 1 μm or narrower in width (Again, see, for example, the OYO BUTURI publication.
Similar techniques known to those skilled in the art include annealing in a non-oxidizing atmosphere above 800° C. and a performing a heat treatment in a low pressure hydrogen atmosphere. It is expected that annealing in a non-oxidizing atmosphere above 800° C. rounds the trench corners and that the heat treatment in the low pressure hydrogen atmosphere smoothes the trench inner surfaces roughened by reactive ion etching (hereinafter referred to as “RIE”) (See Japanese Patent Publication JP P Hie. 10 (1998)—12716 A (claim 1), and Japanese Patent 3424667 (Paragraphs 0028 and 0029)). It is also described in Japanese Patent 3424667 that the residues in the trenches are removed by washing with a mixture of sulfuric acid and hydrogen peroxide and by subsequent washing with hydrofluoric acid. Also described is a technique for controlling the taper angle of trench inner walls in forming trenches by using first an etching gas mixture of a hydrogen halide and oxygen and, then, a gas mixture of a halogen containing gas and oxygen. Smoothing the trench inner surfaces also is described. However, the problems described above also are posed on the taper angle control and the trench inner surface smoothing when the trench is 2 μm or narrower in width and especially when the trench is 1 μm or narrower in width (See Japanese Patent Publication JP-P 2002-141407 A (Claim 7, Paragraph 0043)).
Summarizing the problems described above, it has been made clear that some residues remain unremoved from the trench when subjected only to a heat treatment in a low pressure hydrogen atmosphere, or other treatment techniques described above, when the trench is 2 μm or narrower in width and especially when the trench is 1 μm or narrower in width, and that these conventional techniques are not always satisfactory for washing the inside of the trench. The conventional techniques exhibit a very weak or no effect for removing the residues other than the SiOX residues such as amorphous silicon and the particles of oxide films peeled off. Adversely affected by the difficulties caused in removing the residues, it is also difficult for the conventional technique to round the trench corners. Therefore, how to thoroughly remove the difficult residues has posed a serious problem for trench downsizing.
In view of the foregoing, it would be desirable to provide a method for manufacturing semiconductor devices that facilitates adequate and proper removal of etching residues in the trenches and proper rounding of trench corners when the trench width is 2 μm or narrower in width and even when the trench width is 1 μm or narrower in width.